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AS5506/2
SAE Architecture Analysis and Design Language (AADL) Annex Volume 2: Annex B: Data Modeling Annex Annex D: Behavior Model Annex Annex F: ARINC653 Annex
SAE Architecture Analysis and Design Language (AADL) Annex Volume 2: Annex B: Data Modeling Annex Annex D: Behavior Model Annex Annex F: ARINC653 Annex
有效
【范围】 (1) The SAE Architecture Analysis & Design Language (referred to in this document as AADL) is a textual and graphical language used to design and analyze the software and hardware architecture of performance-critical real- time systems. These are systems whose operation strongly depends on meeting non-functional system requirements such as reliability, availability, timing, responsiveness, throughput, safety, and security. AADL is used to describe the structure of such systems as an assembly of software components mapped onto an execution platform. It can be used to describe functional interfaces to components (such as data inputs and outputs) and performance-critical aspects of components (such as timing). AADL can also be used to describe how components interact, such as how data inputs and outputs are connected or how application software components are allocated to execution platform components. The language can also be used to describe the dynamic behavior of the runtime architecture by providing support to model operational modes and mode transitions. The language is designed to be extensible to accommodate analyses of the runtime architectures that the core language does not completely support. Extensions can take the form of new properties and analysis specific notations that can be associated with components and are standardized themselves. (2) AADL was developed to meet the special needs of performance-critical real-time systems, including embedded real-time systems such as avionics, automotive electronics, or robotics systems. The language can describe important performance-critical aspects such as timing requirements, fault and error behaviors, time and space partitioning, and safety and certification properties. Such a description allows a system designer to perform analyses of the composed components and systems such as system schedulability, sizing analysis, and safety analysis. From these analyses, the designer can evaluate architectural tradeoffs and changes. (3) AADL supports analysis of cross cutting impact of change in the architecture along multiple analysis dimensions in a consistent manner. Consistency is achieved through automatic generation of analysis models from the annotated architecture model. AADL is designed to be used with generation tools that support the automatic generation of the source code needed to integrate the system components and build a system executive from validated models. This architecture-centric approach to model-based engineering permits incremental validation and verification of system models against requirements and implementations against systems models throughout the development lifecycle. (4) This document consists of three annexes to the SAE AADL standard that provides guidance on a standard way of associating data models expressed in other data modeling notations such as UML or ASN.1 with architecture models expressed in AADL, enables modeling of component and component interaction behavior in a state-machine based annex sublanguage, and provides guidance on a standard way of representing ARINC653 standard compliant partitioned embedded system architectures in AADL models.strRefField
【与前一版的变化】

引用文件/被引文件

Architecture Analysis & Design Language (AADL)
Architecture Analysis & Design Language (AADL) Annex Volume 1
IEEE Standard Glossary of Software Engineering Terminology
AERONAUTICAL RADIO

包含图表

Sender Behavior Spec
Client Server Behavi
ARINC653 Module (wit
Partition and its As
Partition and its As
Multi-processor syst
ARINC653 Process ins
ARINC653 Process ins
ARINC653 Inter-parti
ARINC653 Inter-parti
ARINC653 Buffer Comm
ARINC653 Blackboard
ARINC653 Event Commu
ARINC653 Semaphore U
Binding of ARINC653
Modeling of Devices
TABLE 1
TABLE 2
Intra- and Inter-par
Two Module Example

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