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基本信息

【范围】

This document is a result of the desire for interoperability of modules on a Pi-Bus. This standard is a stand alone document that used the Very High Speed Integrated Circuit (VHSIC) Phase 2, Interoperability Standard PI-Bus Specification 2.2, as a starting point. 1.1 Purpose: This standard defines a bus and module interface to the Pi-Bus. This standard specifies the requirements/functions for the Pi-Bus side of a Bus Interface Unit (BIU) needed to facilitate the interoperability of modules on a Pi-Bus for avionics systems. The corresponding software/device side interface requirements are not specified in this standard. 1.2 Field of Application: The Pi-Bus is intended to provide a Master-Slave communications path for transferring digital messages between a set of up to 32 modules residing on a single backplane. 1.3 Classification: Bus configurations and modules which conform to this standard are specified in Table 1: {0392507197e6779b2868a29a8e84f5fb.jpg} 1.3 (Continued): Buses and modules shall be classified according to their maximum capabilities. Bus sequences shall be classified according to the Type or Class of transfer actually used. All modules and buses shall be capable of operating in Type 16, Class ED mode. 1.3.1 16 ED Mode: A 16 ED module shall be configurable to operate on one of two separate 16 ED buses. The module shall be capable of participating in 16 ED Vie and message sequences. 1.3.2 32 EC Nonmixed Mode: A 32 EC nonmixed mode module shall be configurable to operate in either a 16 ED configuration or a 32 EC nonmixed mode configuration. In a 16 ED configuration, it shall operate as a 16 ED module. In the 32 EC nonmixed mode configuration, it shall operate on a single error correction bus (which contains only modules operating in 32 EC nonmixed mode) using 32 EC Vie and message sequences. 1.3.3 32 EC Mixed Mode: A 32 EC mixed mode module shall be configurable to operate in one of two configurations. The first configuration is the 32 EC nonmixed mode configuration. In the second configuration, it shall be capable of performing 16 ED Vie, 16 ED message and 32 EC message sequences, to allow interoperation of 16 ED modules and 32 EC mixed mode modules. In this configuration, the module shall be configurable to operate on one of two separate 16 ED buses as well as a 32 EC bus. A 32 EC mixed mode module operating in the second configuration will not be interoperable with a 32 EC nonmixed mode module operating in the 32 EC configuration. This configuration shall use the format bit, DF<0>, and DC<0> to determine which message Type (i.e., 16 ED or 32 EC) sequence to perform.strRefField

【与前一版的变化】

包含缩略语

A：
AB：
ABn：
ACK：
AS：
AT：
AWM0：
AWM1..4：
AWS：
AWT：
B：
BIT：
BIU：
BR：
CT：
CTC：
D：
DA0：
DAn：
DC：
DF：
Dn：
DZ：
EC：
ED：
EH：
F：
H：
HAn：
HA0：
Hn：
H0：
HWA：
HWB：
HWC0：
HWC1：
HZ：
ID：
Io1：
MID：
MIP：
MS：
NAK：
NS：
NT：
RC：
RCG：
RCW：
RCW0：
RCW1：
S：
SH：
SO：
SS：
SSR：
SSW：
Tf：
Tr：
Tpdlh：
V：
VC0：
VHSIC：
Vih：
Vi：
Vn：
Vol：
VP0..8：
VZn：
W：

引用文件/被引文件

VHSIC Phase 2

Interoperability Standard PI-Bus

Ver. 2.2

Specification

15 Mar 90

GJB/Z 122-99

机载电子设备设计准则

AIR4980

MODULAR AVIONICS BACKPLANE FUNCTIONAL REQUIREMENTS AND CONSENSUS ITEMS (MABFRACI)

AIR4903

Pi-Bus Handbook

相关标准

·GJB 76.2-85

航空用聚酰亚胺绝缘电线电缆镀银铜芯PI/F46绝缘PI漆护层电线

·GJB 78.3-85

航空用聚酰亚胺薄膜绝缘电线电缆镀银铜芯PI/F46绝缘F4生带护套电线

·GJB 76.4-85

航空用聚酰亚胺薄膜绝缘电线电缆铝芯PI/F46薄膜绝缘F4生带护套电线

·HB 7664-99

并行互连(PI)总线

·GJB 78.5-85

航空用聚酰亚胺薄膜绝缘电线电缆镀银铜合金导体PI/F46绝缘FI漆护层电线

·AIR4013B

Multiplex Data Bus Networks for MIL-STD-1760 Stores

·AIR4288

Linear Token Passing Multiplex Data Bus User's Handbook

·AS4074A

Linear Token Passing Multiplex Data Bus

·AS4111

Validation Test Plan for the Digital Time Division Command/Response Multiplex Data Bus Remote Terminals

·AS4112

PRODUCTION TEST PLAN FOR THE DIGITAL TIME DIVISION COMMAND/RESPONSE MULTIPLEX DATA BUS REMOTE TERMINALS

包含图表

Bus Configuration Ty	Conceptual Mode of B	Pi-Bus Signal line R
Pi-Bus Cycle Types a	Interpretation of Cy	Acknowledge Line Set
Pi-Bus Signal Pairin	Signal Partitioning	Set-up and Hold Timi
Signal Output Test C	Output Signal Timing	Pi-Bus Communication
Pi-Bus Protocol Stat	Pi-Bus Protocol Stat	Generic Pi-Bus Messa
Header Word A Format	Mixed Mode Data Form	Message Type Codes
AT (Access Type) Cod	Single Slave Acknowl	Multiple Slave Statu
Multiple Slave Statu	Multiple Slave Ackno	Multiple Slave Ackon
Bus State Definition	Vie Sequence	Module Vie Code Form
Module Vie Code Form	Parameter Write Sequ	Parameter Write Sequ
Parameter Write Sequ	Parameter Write Sequ	Parameter Write Head
Parameter Write Mess	Parameter Write Mess	Block Message - SH S
Bus State H0 to Bus	Bus State D0 to Bus	Block Message - SH S
Bus State H0 to Bus	Bus State D0 to Bus	Block Message - Shor
Block Message - Shor	Block Message - Shor	Bus State H0 to Bus
Bus State D0 to Bus	Bus State H0 to Bus	Bus State HA3 to Bus
Bus State H0 to Bus	Bus State D0 to Bus	Bus State H0 to Bus
Bus State D0 to Bus	Block Message-Extend	Block Message-Extend
Block Message-Extend	Bus Interface Messag	Bus Interface Messag
Bus State H0 to Bus	Bus State D0 to Bus	Bus Interface Messag
Bus Interface Messag	Datagram Message-Sho	Datagram Message-Sho
Datagram Message (No	Datagram Message (No	Acknowledged Datagra
Acknowledged Datagra	Acknowledged Datagra	Datagram Message-Ext
Datagram Message-Ext	Datagram Message (No	Datagram Message (No
Acknowledged Datagra	Bus State H0 to Bus	Bus State Dz to Bus
Bus State H0 to Bus	Bus State Dz to Bus	Suspend - Short Data
Suspend - Short Data	Suspend - Extended D	Suspend - Extended D
Suspend - Type 16 ED	Suspend - Type 32 EC	Suspend - Type 16 ED
Suspend - Type 32 EC	Suspend - Type 16 ED	Suspend - Type 32 EC
Abort Sequence	Data link Address Sp	Control Register Wor
Module Capabilities	Vie Interval A Regis	Vie Interval B Regis
Vie Priority Registe	Logical Slave Identf	Interpretation for U
Slave Response to Cy	Cycle Type Deviation	Sequence Error Respo
Semantic Errors